The present invention relates generally to magneto-resistive memory devices, and more particularly, to sense amplifiers for magneto-resistive memory devices.
Digital memories of various kinds are used extensively in computer and computer system components, in digital processing systems and the like. One such kind of memory can be formed, to considerable advantage, based on the storage of digital bits as alternative states of magnetization in magnetic materials in each memory cell, typically thin film materials. In ferromagnetic thin film memories, the states of the memory cells based on magnetization direction are determined through magneto-resistive properties of the thin film. To read the state of a ferromagnetic thin film memory, a sense current is typically provided through the ferromagnetic thin film elements of a selected memory cell, and a resulting voltage signal is sensed by an electronic circuit such as a sense amplifier.
The magneto-resistance of a ferromagnetic thin film element typically only changes a few percent when exposed to a magnetic field. Accordingly, the resulting signal level generated when a sense current is passed through the ferromagnetic thin film element is typically quite small. Many sense amplifiers cannot reliably operate at these low signal levels for a variety of reasons including the internal offsets of the amplifier, noise, etc. To compensate for these limitations, the sense current must often be increased to increase the signal levels that are produced and provided to the sense amplifier. This, however, increases the power and sometimes reduces the speed of the memory, particularly for memory architectures where multiple memory cells are accessed simultaneously. Accordingly, a need exists for a high-speed sense amplifier that reliably operates at low signal levels, and in particular, those signal levels that are produced by magneto-resistive memory devices.
The present invention overcomes many of the disadvantages of the prior art by providing a magneto-resistive memory that includes a high-speed sense amplifier that can reliably operate at low signal levels. To achieve this, the sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is preferably controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.
In one illustrative embodiment of the present invention, a magneto-resistive memory is provided that has a first magneto-resistive bit with a first end and a second end and a second magneto-resistive bit with a first end and a second end. The first end of the first magneto-resistive bit is coupled to a first bit line and the first end of the second magneto-resistive bit is coupled to a second bit line. The second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit are selectively coupled to a predetermined reference voltage such as ground via one or more selection switches. The selection switches allow one or more memory cells to be selected during a read or write operation.
The first magneto-resistive bit and the second magneto-resistive bit are preferably written into opposite resistive states. Thus, when a sense current is provided to the first and second bit lines, and the one or more selection switches are enabled to ground the second end of the first magneto-resistive bit and the second magneto-resistive bit, a differential voltage is generated between the first bit line and the second bit line. The sense amplifier then senses and amplifies this differential voltage.
The offset cancellation of the sense amplifier can be achieved in a variety of ways. In an input offset storage embodiment, one or more coupling capacitors couple the differential voltage from the first and second bit lines to the inputs of a differential amplifier. During offset cancellation, one or more switches selectively connect the inputs of the differential amplifier to the outputs of the differential amplifier. Also, the inputs of the one or more coupling capacitors are disconnected from the first and second bit lines, and connected to a predetermined reference voltage such as ground. In this configuration, a charge is stored on the one or more coupling capacitors that compensates for internal offsets of the amplifier.
Once the coupling capacitors are charged, the offset cancellation is disabled. When the offset cancellation is disabled, the inputs of the differential amplifier are disconnected from the outputs of the differential amplifier, and the inputs of the one or more coupling capacitors are connected to the first and second bit lines of the magneto-resistive memory. Because the internal offsets of the differential amplifier are already stored on the coupling capacitors, the resulting output signal of the differential amplifier is substantially free of the internal offsets, thereby allowing the reliable amplification of relatively small signals.
Instead of connecting the coupling capacitors to a predetermined reference voltage during offset cancellation, it is contemplated that a differential voltage having the opposite polarity to the differential voltage between the first and second bit lines may be provided to the coupling capacitors. This may cause the coupling capacitors to store a charge that not only cancels out the internal offsets of the differential amplifier, but also includes a charge that corresponds to the opposite polarity of the desired differential voltage signal. Once the offset cancellation is disabled, the differential voltage generated between the first and second bit lines is provided to the coupling capacitors. This embodiment may produce about a two times amplification in the differential voltage signal, as seen at the inputs of the differential amplifier, thereby further increasing the ability of the sense amplifier to reliably amplify small signals.
In an output offset storage embodiment, the one or more coupling capacitors are coupled to the outputs of the differential amplifier. Further, the one or more switches that enable the offset cancellation selectively connect the output of the coupling capacitors to a predetermined reference voltage such as ground, and selectively connect the inputs of the differential amplifier to a predetermined voltage such as ground. In this configuration, and like above, a charge is stored on the one or more coupling capacitors that corresponds to the internal offsets of the amplifier.
Once the coupling capacitors are charged, the offset cancellation may be disabled, which disconnects the outputs of the coupling capacitors from the predetermined reference voltage, and disconnects the inputs of the differential amplifier from the predetermined reference voltage. The inputs of the differential amplifier are also connected to the first and second bit lines of the magneto-resistive memory. Because the internal offsets of the differential amplifier are already stored on the coupling capacitors, the resulting output signal at the output of the coupling capacitors is substantially free of the internal offsets, thereby allowing the reliable amplification of relatively small signals.
Instead of connecting the outputs of the coupling capacitors to a predetermined reference voltage during offset cancellation, it is contemplated that a differential voltage having the opposite polarity of the differential voltage generated between the first and second bit lines may be provided to the coupling capacitors. The differential voltage having the opposite polarity of the differential voltage generated between the first and second bit lines may also be provided to the inputs of the differential amplifier. This may cause the coupling capacitors to store a charge that not only cancels out the internal offsets of the differential amplifier, but also includes a charge that corresponds to the opposite polarity of the desired differential voltage. Once the offset cancellation is disabled, the differential voltage generated between the first and second bit lines may be provided to the inputs of the differential amplifier. This may produce about a two times amplification in the differential voltage, as seen at the outputs of the coupling capacitors, thereby further increasing the ability of the sense amplifier to reliably amplify small signals.
The output of the sense amplifier is preferably provided to a storage element, such as a latch. The latch may store the data state read from the magneto-resistive memory. In an illustrative embodiment, the latch includes a pair of cross-coupled inverters, where each of the cross-coupled inverters has an input terminal, an output terminal, a power supply terminal and a ground terminal. A pair of switches are provided for selectively disconnecting the power supply terminal from a power supply voltage and/or the ground terminal from ground. The illustrative latch further includes at least one switch for selectively connecting the output of the sense amplifier to at least one of the output terminals of the cross-coupled inverters. Finally, the illustrative latch further includes a reset switch for selectively connecting together the output terminals of the cross-coupled inverters.
During operation, a control block selectively disconnects the power supply terminal and the ground terminal (collectively called the power supply terminals) of each of the cross-coupled inverters. The control block then enables the at least one switch of the latch to allow the output signal of the amplifier to set the voltage levels of at least one of the output terminals of the cross-coupled inverters. The control block then disables the at least one switch of the latch to prevent the output signal of the amplifier from setting the voltage levels of the output terminals of the cross-coupled inverters. The control block then connects the power supply terminals of each of the cross-coupled inverters of the latch, which sets the latch to desired state. The desired state is preferably read from the latch. The control block again disconnects the power supply terminals of each of the cross-coupled inverters. Finally, the control block resets the state of the latch by selectively connecting the output terminals of the cross-coupled inverters via the reset switch of the latch.